MT8941B - Advanced T1/CEPT Digital Trunk PLL

Product Overview

Zarlink Semiconductor

Datasheet Details

Part number	MT8941B
Manufacturer	Zarlink Semiconductor
File Size	491.08 KB
Description	Advanced T1/CEPT Digital Trunk PLL
Datasheet	MT8941B Datasheet
Additional preview pages of the MT8941B datasheet.

Product details

Description

The MT8941B is a dual digital phase-locked loop providing the timing and synchronization signals for the T1 or CEPT transmission links and the ST-BUS.

The first PLL provides the T1 clock (1.544 MHz) synchronized to the input frame pulse at 8 kHz.

Features

Provides T1 clock at 1.544 MHz locked to an 8 kHz reference clock (frame pulse) Provides CEPT clock at 2.048 MHz and ST-BUS clock and timing signals locked to an internal or external 8 kHz reference clock Typical inherent output jitter (unfiltered)= 0.07 UI peak-to-peak Typical jitter attenuation at: 10 Hz=23 dB,100 Hz=43 dB, 5 to 40 kHz ≥ 64 dB Jitter-free “FREE-RUN” mode Uncommitted two-input NAND gate Low power CMOS technology Ordering Information MT8941BE 24 Pin PDIP Tube.

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Published: Oct 9, 2005 |