PDSP16488A Datasheet PDF (Single Chip 2D Convolver with Integral Line Delays) | Download Mitel Networks Corporation PDSP16488A

PDSP16488A - Single Chip 2D Convolver with Integral Line Delays

Description

Pixel data input to the first line delay (most significant byte in 16-bit mode).

Pixel data input to the second group of line delays.

(least significant byte in 16-bit mode).

Features

s The PDSP16488A is a replacement for the PDSP16488 (see Note below) s 8 or 16-bit Pixels with rates up to 40 MHz s Window Sizes up to 838 with a Single Device s Eight Internal Line Delays s Supports Interlace and Frame-to-Frame Operations s Coefficients Supplied from an EPROM or Remote Host s Expandable in both X and Y for Larger Windows s Gain Control and Pixel Output Manipulation s 84-pin PGA or 132-pin QFP Package Options Note: PDSP16488A devices are not guaranteed to cascade with PDSP16488.

Datasheet Details

Part number	PDSP16488A
Manufacturer	Mitel Networks Corporation
File Size	412.58 KB
Description	Single Chip 2D Convolver with Integral Line Delays
Datasheet	PDSP16488A Datasheet
Additional preview pages of the PDSP16488A datasheet.

📁 Similar Datasheet

PDSP16488A - Single Chip 2D Convolver (Zarlink Semiconductor)

PDSP16488AMA - Single Chip 2D Convolver (Zarlink Semiconductor)

PDSP1601 - ALU and Barrel Shifter (Zarlink Semiconductor)

PDSP1601A - ALU and Barrel Shifter (Zarlink Semiconductor)

PDSP16112 - 16 X 12 BIT COMPLEX MULTIPLIER (Zarlink Semiconductor)

PDSP16112A - 16 X 12 BIT COMPLEX MULTIPLIER (Zarlink Semiconductor)

PDSP16116 - 16 by 16 Bit Complex Multiplier (Zarlink Semiconductor)

PDSP16116A - 16 by 16 Bit Complex Multiplier (Zarlink Semiconductor)

PDSP16116MC - 16 by 16 Bit Complex Multiplier (Zarlink Semiconductor)

PDSP16256 - Programmable FIR Filter (Zarlink Semiconductor)

Full PDF Text Transcription

Click to expand full text

PDSP16488A Single Chip 2D Convolver with Integral Line Delays Advance Information Supersedes version in 1996 Media IC Handbook, HB4599-1.0 and the PDSP16488A MA data sheet, DS3742 DS3713 - 6.4 December 1997 The PDSP16488A is a fully integrated, application specific, image processing device. It performs a two dimensional convolution between the pixels within a video window and a set of stored coefficients. An internal multiplier accumulator array can be multi-cycled at double or quadruple the pixel clock rate. This then gives the window size options listed in Table 1. An internal 32kbit RAM can be configured to provide either four or eight line delays. The length of each delay can be programmed to the users requirement, up to a maximum of 1024 pixels per line.

Published: Mar 22, 2005 |