MH89760B Datasheet | Mitel Networks

Features - - - - - - - - - - - - - - - - plete interface to a bidirectional T1 link D3/D4 or ESF framing and SLC-96 patible Two frame elastic buffer with 32µ s jitter buffer Insertion and detection of A, B, C, D bits Signalling freeze, optional debounce Selectable B8ZS, jammed bit (ZCS) or no zero code suppression Yellow and blue alarm signal capabilities Bipolar violation count, FT error count, CRC error count Frame and superframe sync. signals, Tx and Rx Per channel, overall, and remote loop around 8 k Hz synchronization output Digital phase detector between T1 line and STBUS ST-BUS patible Pin patible with the MH89760 Inductorless clock recovery Loss of Signal (LOS) indication Available in standard, narrow and surface mount formats MH89760B MH89760BN MH89760BS ISSUE 5 May 1995 Ordering Information 40 Pin DIL Hybrid 1.3" row pitch 40 Pin DIL Hybrid 0.8" row pitch 40 Pin Surface Mount Hybrid 0° C to 70° C Description The MH89760B is a plete T1 interface solution, meeting the Extended Super Frame (ESF), D3/D4 and SLC-96 formats. The MH89760B interfaces to the DS11.544 Mbit/sec digital trunk. The MH89760B is a pin-patible enhancement of the MH89760, permitting the removal of the tuneable inductor and inclusion of the external NAND gate used for generating Rx D. Applications - - - DS1/ESF digital trunk interfaces puter to PBX interfaces (DMI and CPI) High speed puter to puter data links Tx SF C2i F0i Rx SF DSTo DSTi CSTi0 CSTi1 CSTo C1.5i ST-BUS Timing Circuitry 1544-2048 Two Frame Elastic Buffer DS1 LINK INTERFACE 2048 - 1544 Converter Serial Control Interface Transmitter Rx FDLClk Rx FDL Tx FDLClk Tx FDL OUTA OUTB Rx A Rx T LOS Rx R Rx B Data Interface Receiver ABCD Signalling RAM VDD XCtl XSt Control Logic Phase Detector Clock Extractor DS1 Counter E1.5o E8Ko VSS Figure 1 - Functional Block Diagram 4-55 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC LOS NC Tx FDL NC Tx FDLClk VSS Rx FDLClk DSTo Rx FDL OUTB C1.5i Rx SF Tx SF OUTA NC NC NC...