MH89770 Datasheet | Mitel Networks

Features - - - - - - - - - - - - - - - - plete interface to a bidirectional T1 link D3/D4 or ESF framing and SLC-96 patible Two frame elastic buffer with jitter tolerance improved to 156UI Insertion and detection of A, B, C, D bits Signalling freeze, optional debounce Selectable B8ZS, jammed bit (ZCS) or no zero code suppression Yellow and blue alarm signal capabilities Bipolar violation count, FT error count, CRC error count Frame and superframe sync. signals, Tx and Rx Per channel, overall, and remote loop around 8 k Hz synchronization output Digital phase detector between T1 line and ST-BUS ST-BUS patible Pin patible with the MH89760BN/BS Inductorless clock recovery Loss of Signal (LOS) indication Available in standard, narrow and surface mount formats MH89770N MH89770S ISSUE 2 March 1995 Ordering Information 40 Pin DIL Hybrid 0.8" row pitch 40 Pin Surface Mount Hybrid 0° C to 70° C Applications - - - DS1/ESF digital trunk interfaces puter to PBX interfaces (DMI and CPI) High speed puter to puter data links Description The MH89770 is a plete T1 interface solution, meeting the Extended Super Frame (ESF), D3/D4 and SLC-96 formats. The MH89770 interfaces to the DS1 1.544 Mbit/sec digital trunk and has the capability of meeting ACCUNET®1 T1.5 wander tolerance (138 UI). The MH89770 is a pin-patible enhancement of the MH89760B. 1. ACCUNET ® T1.5 is a registered trademark of AT & T. Tx SF C2i F0i Rx SF DSTo DSTi CSTi0 CSTi1 CSTo C1.5i ST-BUS Timing Circuitry Two Frame Elastic Buffer with Slip Control DS1 LINK INTERFACE 2048 - 1544 Converter Serial Control Interface Transmitter Rx FDLClk Rx FDL Tx FDLClk Tx FDL OUTA OUTB Rx A Rx T LOS Rx R Rx B Data Interface Receiver ABCD Signalling RAM VDD XCtl XSt Control Logic Phase Detector Clock Extractor DS1 Counter E1.5o E8Ko VSS Figure 1 - Functional Block Diagram 4-125 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC LOS NC Tx FDL NC Tx FDLClk VSS Rx FDLClk DSTo Rx FDL OUTB C1.5i Rx SF Tx SF OUTA NC NC...