M5M4V4265CJ-7S Datasheet | Mitsubishi Electric

MITMSUITBSIUSHBISLHSIIs LSIs M5M4V4265CJM,5TMP4V-452,6-56C,J-,7TP,--55,-S6,,--76,-5SS,,--67SS,-7S EDOED(HOY(PHEYRPPEARGPEA)GMEO) DMEO4D1E9431094-3B0I4T-B(2IT62(124642-1W44O-WRDORBDY 1B6Y-B1I6T-)BDITY)NDAYMNIACMRICAMRAM DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs with EDO mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal puter graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. The lower supply (3.3V) operation, due to the optimization of transistor structure, provides low power dissipation while maintaining high speed operation. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up...