M5M4V4265CJ Datasheet | Mitsubishi Electric

MITSUBISHI LSIs MITSUBISHI LSIs M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S M5M4V4265CJ,TP-5,-6,-7,-5S,-6S,-7S EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM DESCRIPTION This is a family of 262144-word by 16-bit dynamic RAMs with EDO mode fuction, fabricated with the high performance CMOS process, and is ideal for the buffer memory systems of personal puter graphics and HDD where high speed, low power dissipation, and low costs are essential. The use of double-layer metalization process technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. The lower supply (3.3V) operation, due to the optimization of transistor structure, provides low power dissipation while maintaining high speed operation. Multiplexed address inputs permit both a reduction in pins and an increase in system densities. Self or extended refresh current is low enough for battery back-up application. This device has 2CAS and 1W terminals with a refresh cycle of 512 cycles every 8.2ms. PIN CONFIGURATION (TOP VIEW) (3.3V)VCC DQ1 DQ2 DQ3 DQ4 (3.3V)VCC DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS(0V) DQ16 DQ15 DQ14 DQ13 VSS(0V) DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A8 A7 A6 A5 A4 VSS(0V) DQ8 10 Features Type name M5M4V4265CXX-5,-5S M5M4V4265CXX-6,-6S M5M4V4265CXX-7,-7S RAS CAS Address access access access time time time (max.ns) (max.ns) (max.ns) Power OE Cycle dissipaaccess time tion time (max.ns) (min.ns) (typ.m W) NC 11 NC 12 W 13 RAS 14 NC 15 A0 16 A1 17 A2 18 A3 19 (3.3V)VCC 20 50 60 70 13 15 20 25 30 35 13 15 20 90 110 130 408 363 333 XX=TP,J Standard 40 pin SOJ, 44 pin TSOP (II) Single 3.3±0.3V supply Low stand-by power dissipation CMOS Input level 1.8m W (Max) CMOS Input level 360µW (Max) - Operating power dissipation M5M4V4265CXX-5,-5S 486m W (Max) M5M4V4265CXX-6,-6S 432m W (Max)...