M5M54R04J-12 Datasheet | Mitsubishi Electric

MITSUBISHI LSIs M5M54R04J-12,-15 1997.11.20 Rev.F 4194304-BIT (1048576-WORD BY 4-BIT) CMOS STATIC RAM DESCRIPTION The M5M54R04J is a family of 1048576-word by 4-bit static RAMs, fabricated with the high performance CMOS silicon gate PIN CONFIGURATION (TOP VIEW) A0 1 A1 2 address A2 3 lead package(SOJ). inputs A3 4 These device operate on a single 5V supply, and are directly A4 5 chip select TTL patible. They include a power down feature as well. S 6 input data inputs/ DQ1 7 Features outputs (5V) VCC 8 - Fast access time M5M54R04J-12 - - - - 12ns(max) (0V) GND 9 M5M54R04J-15 - - - - 15ns(max) data inputs/ DQ 2 10 - Low power dissipation Active - - - - - - - - - - 450m W(typ) outputs W 11 write control Stand by - - - - - - - - - - 5m W(typ) input A5 12 - Single +5V power supply A6 13 - Fully static operation : No clocks, No refresh address A7 14 - mon data I/O inputs A8 15 - Easy memory expansion by S A9 16 - Three-state outputs : OR-tie capability - OE prevents data contention in the I/O bus - Directly TTL patible : All inputs and outputs Outline The M5M54R04J is offered in a 32-pin plastic small outline J- process and designed for high speed...