M65617 Datasheet | Mitsubishi Electric

MITSUBISHI ICs (TV) M65617SP PICTURE-IN-PICTURE SIGNAL PROCESSING DESCRIPTION This system is an NTSC system Pin P system that acmodates subscreen posite input and main screen Y/C input. It is a semiconductor IC circuit having a built-in 96K bit field memory and an analog circuit, which permits a low-cost and pact system configuration. PIN CONFIGURATION (TOP VIEW) AVss3 (vcxo) VCXO out VCXO in FILTER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 AVssf (ana) 51 Cin 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 TESTEN Yin TEST9 Y-PIP TEST8 C-PIP AVdd4 (da) C-PIPin AVss4 (da) Y-PIPin ADJ-Ysub Yout-sub ADJ-Csub Cout-sub DVss3 (ram) DVdd3 (ram) SWMG/TEST7 VD/CSYNC/TEST6 HD/TEST5 SWM/TEST4 MCK fsc/TEST3 BGP(m)/TEST2 DVdd2 Features BIAS AVdd3 (vcxo) AVdd2 (m) Vin (m) Vrt (m) Vrb (m) AVss2 (m) AVdd1 (s) Vin (s) Vrt (s) Vrb (s) AVss1 (s) RESET DVss1 DVdd1 BGP(s)/TEST0 - - - - - - - - - Built-in field memory 96K bit for PIP Built-in luminance signal vertical filter No. of subscreen displays: 1 (two sizes, 1/9 and 1/16, can be selected from.) No. of subscreen samples (1/9 - 1/16 sizes) No. of quantization bits: 6 for all Y, B-Y and R-Y No. of horizontal picture elements: 171(Y), 28.5 (B-Y, R-Y) No. of vertical lines: 69/52 Subscreen frame display ON/OFF Built-in analog circuits such as sync chip clamp, VCXO, and analog switch Built-in 2 channels of 8 bit A/D converter (for main signal burst lock and PIP sub signal) Built-in two channels of 8 bit D/A converter (luminance and chroma signals) I2C bus control Controls: display ON/OFF, display size selection, setting of display position, frame ON/OFF, setting of frame level, selection of frame animation/field still image, setting of Y delay amount, color level, tint, black level, etc. M65617SP APPLICATION SCK CSYNC(s)/TEST1 ACK REMENDED OPERATING CONDITION Supply voltage range........................................................3.1 to 3.5V Operating...