V58C265404S Overview
The V58C265404S is a four bank DDR DRAM organized as 4 banks x 4Mbit x 4. The V58C265404S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS.
V58C265404S Key Features
- CLK Cycle Time (ns) -6
- Power Std
- Temperature Mark