V58C265804S Overview
The V58C265804S is a four bank DDR DRAM organized as 4 banks x 2Mbit x 8. The V58C265804S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS.
V58C265804S Key Features
- CLK Cycle Time (ns) -6
- Power Std
- Temperature Mark