V58C3643204SAT Overview
The V58C3643204SAT is a four bank DDR DRAM organized as 4 banks x 512K x 32. The V58C3643204SAT achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS.
V58C3643204SAT Key Features
- CLK Cycle Time (ns) -45
- Power -60
- Temperature Mark
- A7, AP, BA0, BA1 Row Addresses A0
- A10, BA0, BA1