V58C365164S Overview
The V58C365164S is a four bank DDR DRAM organized as 4 banks x 1Mbit x 16. The V58C365164S achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock. I/O transactions are possible on both edges of DQS.
V58C365164S Key Features
- 4 banks x 1Mbit x 16 organization
- High speed data transfer rates with system frequency up to 275 MHz
- Data Mask for Write Control (DM)
- Four Banks controlled by BA0 & BA1
- Programmable CAS Latency: 2, 2.5, 3
- Programmable Wrap Sequence: Sequential or Interleave
- Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type
- Automatic and Controlled Precharge mand
- Suspend Mode and Power Down Mode
- Auto Refresh and Self Refresh