V62C5181024 Overview
The V62C5181024 is a 1,048,576-bit static random-access memory organized as 131,072 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures.
V62C5181024 Key Features
- 32-pin TSOP (Standard)
- 32-pin 600 mil PDIP
- 32-pin 440 mil SOP (525 mil pin-to-pin)
- Access Time (ns) 35
- Power LL
- Temperature Mark Blank I