V62C51864 Overview
The V62C51864 is a 65,536-bit static random access memory organized as 8,192 words by 8 bits. It is built with MOSEL VITELIC’s high performance CMOS process. Inputs and threestate outputs are TTL patible and allow for direct interfacing with mon system bus structures.
V62C51864 Key Features
- TTL Standby: 2 mA (Max.)
- CMOS Standby: 15 mA (Max.) s Fully static operation s All inputs and outputs directly patible s Three state outputs s Ul
- 28-pin 600 mil PDIP
- 28-pin 330 mil SOP (450 mil pin-to-pin)
- Access Time (ns) 35
- Power LL
- Temperature Mark Blank I