MPC9608 Overview
The MPC9608 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. This enables nested clock designs with near-zero insertion delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed from traditional fanout buffers.
MPC9608 Key Features
- 1:10 outputs LVCMOS zero-delay buffer
- Single 3.3 V supply Supports a clock I/O frequency range of 12.5 to 200 MHz Selectable divide-by-two for one output bank