Motorola 74LS373
74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. The SN54 / 74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.| Part No. | 74LS373 |
|---|---|
| Datasheet | 74LS373 Download |
| Manufacturer |  Motorola |
| Description | OCTAL TRANSPARENT LATCH |
| Buy | Stock & Price |
OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS; OCTAL D-TYPE FLIP-FLOP WITH 3-STATE OUTPUT The SN54 / 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54 / A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops.
● Eight Latches in a Single Package
● 3-State Outputs for Bus Interfacing
● Hysteresis on Latch Enable
● Edge-Triggered D-Type Inputs
● Buffered Positive Edge-Triggered Clock
● Hysteresis on Clock Input to Improve Noise Margin
● Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES D0 – D7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) LOADING (Note a) HIGH LOW 0.5 U.L.
● Eight Latches in a Single Package
● 3-State Outputs for Bus Interfacing
● Hysteresis on Latch Enable
● Edge-Triggered D-Type Inputs
● Buffered Positive Edge-Triggered Clock
● Hysteresis on Clock Input to Improve Noise Margin
● Input Clamp Diodes Limit High Speed Termination Effects PIN NAMES D0 – D7 LE CP OE O0 – O7 Data Inputs Latch Enable (Active HIGH) Input Clock (Active HIGH going edge) Input Output Enable (Active LOW) Input Outputs (Note b) LOADING (Note a) HIGH LOW 0.5 U.L.
