74LS373 Overview
745 74LS All lnputs 1Sul 1LSul All Outputs 10Sul 30LSul NOTE: The latch remains transparent to the data inputs while Eis HIGH, and stores the data present one set-up time before the HIGH-to-LOW enable transition. The enable gale has hysteres'1s built in to help minimize problems thai signal and ground noise can cause on the latching operalion.
74LS373 Key Features
- 8-bit transparent latch
- 8-bit positive, edge-triggered
- 3-State output buffers
- mon 3-State Output Enable
- Independent register and 3-State
- 0.4mA l1L
