Signetics 74LS373
The data on the O inputs are transferred to the latch outputs when the Latch Enable (E) input is HIGH. The latch remains transparent to the data inputs while Eis HIGH, and stores the data present one set-up time before the HIGH-to-LOW enable transition.| Part No. | 74LS373 |
|---|---|
| Datasheet | 74LS373 Download |
| Manufacturer |  Signetics |
| Description | Latches/Flip-Flops |
| Buy | Stock & Price |
FEATURES
● 8-bit transparent latch - '373● 8-bit positive, edge-triggered register- '374
● 3-State output buffers
● Common 3-State Output Enable TYPE 74LS373 74S373 74LS374 TYPICAL PROPAGATION DELAY 19ns 10ns 19ns TYPICAL SUPPLV CURRENT (TOTAL) 24mA 105mA 27mA
● Independent register and 3-State 74S374 ans buffer operation 116mA ORDERING CODE DESCRIPTIO N The '373 is an octal transparent latch PACKAGES COMMERCIAL RANGE Vcc = 5V ±5%; TA= 0°C to + 10°c coupled to eight 3-State output buffers. The two sections of the device are Plastic DIP N74LS373N, N74S373N, N74LS374N, N74S374N controlled independently by Latch En- able (E) and Output Enable ( OE) control gates. Plastic SOL-20 N74LS373D, N74S3730, N74LS374D, N74S374D NOTE: For information regarding devices processed to Military Specifications, see the Signetics Military Products Data Manual. I INPUT AND OUTPUT LOADING AND FAN-OUT TABLE * PINS
DESCRIPTION
745 74LS All lnputs 1Sul 1LSul All Outputs 10Sul 30LSul NOTE: Where a 74S unit lead...
