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MC100E193 - ERROR DETECTION/ CORRECTION CIRCUIT

Download the MC100E193 datasheet PDF. This datasheet also covers the MC10E193 variant, as both devices belong to the same error detection/ correction circuit family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (MC10E193-Motorola.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Error Detection/Correction Circuit The MC10E/100E193 is an error detection and correction (EDAC) circuit. Modified Hamming parity codes are generated on an 8-bit word according to the pattern shown in the logic symbol. The P5 output gives the parity of the whole word. The word parity is also provided at the PGEN pin, after Odd/Even parity control and gating with the BPAR input. This output also feeds to a 1-bit shiftable register, for use as part of a scan ring. Used in conjunction with 12-bit parity generators such as the E160, a SECDED (single error correction, double error detection) error system can be designed for a multiple of an 8-bit word.
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