MC10H602
features
D- type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post- latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level.
The 10H version is patible with MECL 10H ECL logic levels. The 100H version is patible with 100K levels.
- 9- Bit Ideal for Byte- Parity Applications
- Flow- Through Configuration
- Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
- Dual Supply
- 3.5 ns Max D to Q
- PNP TTL Inputs for Low Loading
LOGIC SYMBOL
ENECL D0 D1
D2 D3
TTL D4 D5 D6
D7 D8 LEN MR
DQ EN
DQ...
