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MC14522B - Presettable 4-Bit Down Counters

Datasheet Summary

Description

Preset Enable (Pin 3)

If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3.

A high level on the Inhibit input pre

vents the Clock from decrementing the counter.

Features

  • 50% VSS tf VDD VSS ANY Q 50% VSS tPHL 50% Figure 7. Figure 8. VALID tr PRESET ENABLE 90% 50% 10% tPHL tPLH PRESET ENABLE “0” 50% tw 50% VSS tf VDD GND ANY P 50% VSS tsu th VDD VDD Figure 9. Figure 10.

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Datasheet preview – MC14522B

Datasheet Details

Part number MC14522B
Manufacturer Motorola
File Size 272.84 KB
Description Presettable 4-Bit Down Counters
Datasheet download datasheet MC14522B Datasheet
Additional preview pages of the MC14522B datasheet.

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Full PDF Text Transcription

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Presettable 4-Bit Down Counters The MC14522B BCD counter and the MC14526B binary counter are constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. These devices are presettable, cascadable, synchronous down counters with a decoded “0” state output for divide–by–N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide–by–N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.
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