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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC14531B 12-Bit Parity Tree
The MC14531B 12–bit parity tree is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The circuit consists of 12 data–bit inputs (D0 thru D11), and even or odd parity selection input (W) and an output (Q). The parity selection input can be considered as an additional bit. Words of less than 13 bits can generate an even or odd parity output if the remaining inputs are selected to contain an even or odd number of ones, respectively. Words of greater than 12–bits can be accommodated by cascading other MC14531B devices by using the W input.
MC14531B Datasheet
