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MC74AC273 - OCTAL D FLIP-FLOP

Download the MC74AC273 datasheet PDF. This datasheet also covers the MC74ACT273 variant, as both devices belong to the same octal d flip-flop family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • INCHES DIM MIN MAX MIN MAX A 12.65 12.95 0.499 0.510 B 7.40 7.60 0.292 0.299 C 2.35 2.65 0.093 0.104 D 0.35 0.49 0.014 0.019 F 0.50 0.90 0.020 0.035 G 1.27 BSC 0.050 BSC J 0.25 0.32 0.010 0.012 K 0.10 0.25 0.004 0.009 M 0_ 7_ 0_ 7_ P 10.05 10.55 0.395 0.415 R 0.25 0.75 0.010 0.029 G K M Motorola reserves the right to make chan.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MC74ACT273_Motorola.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
MC74AC273 Octal D Flip-Flop ON Semiconductor
MC74AC20 Dual 4-Input NAND Gate ON Semiconductor
MC74AC240 Octal Buffer/Line Driver ON Semiconductor
MC74AC244 Octal Buffer/Line Driver ON Semiconductor
MC74AC245 OCTAL BIDIRECTIONAL TRANSCEIVER ON Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MC74AC20 DUAL 4-INPUT NAND GATE
MC74AC240 OCTAL BUFFER/LINE DRIVER
MC74AC241 OCTAL BUFFER/LINE DRIVER
MC74AC244 OCTAL BUFFER/LINE DRIVER
MC74AC245 OCTAL BIDIRECTIONAL TRANSCEIVER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
( DataSheet : www.DataSheet4U.com ) MC74AC273 MC74ACT273 Octal D FlipĆFlop The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.