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MC88915FN55PLCC - Low Skew CMOS PLL Clock Driver

General Description

on page 11).

state phase and frequency lock.

lock is lost or when the PLL_EN pin is low.

Key Features

  • Five Outputs (QO.
  • Q4) with Output.
  • Output Skew < 500 ps each being phase and frequency locked to the SYNC input.
  • The phase variation from part.
  • to.
  • part between the SYNC and.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Skew CMOS PLL Clock Driver The MC88915 Clock Driver utilizes phase–locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the MC88915 to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 7).