Description
Bus Operation IEEE 1149.1 Test Access Port (JTAG) Mechanical Data Electrical Characteristics Appendix A: List of Memory Maps Appendix B: Buffering and Impedence Matching Index
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Overview ColdFire
Features
- MCF5272 Architecture Version 2 ColdFire Core System Integration Module (SIM) External Bus Interface Chip Select and Wait State Generation System Configuration and Protection Power Management Parallel Input/Output Ports Interrupt Inputs UART Module Timer Module Test Access Port System Design System Bus Configuration MCF5272-Specific Features Physical Layer Interface Controller (PLIC) Pulse-Width Modulation (PWM) Unit Queued Serial Peripheral Interface (QSPI) Universal Serial Bus (USB.
MCF5272 Datasheet
