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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM36F6/D
Advance Information
256KB and 512KB Synchronous Fast Static RAM Module
The MCM36F6 (256KB) is configured as 64K x 36 bits and the MCM36F7 (512KB) is configured as 128K x 36 bits. Both are packaged in a 144–pin dual– in–line memory module (DIMM). Each module uses Motorola’s 3.3 V 64K x 18 bit flow–through BurstRAMs. Address (A), data inputs (DQ, DP), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Write cycles are internally self–timed and initiated by the rising edge of the clock (K) input. This feature provides increased timing flexibility for incoming signals.
MCM36F7 Datasheet
