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MCM6226BB - 128K x 8 Bit Static Random Access Memory

Key Features

  • , 7, 8 6, 7, 8 Notes 5 NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E1. 4. If G goes low coincident with or after W goes low, the output will remain in a high.
  • impedance state. 5. All timings are ref.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM6226B 128K x 8 Bit Static Random Access Memory
MCM6226A 128K x 8 Bit Static Random Access Memory
MCM6227A 1M x 1 Bit Static Random Access Memory
MCM6227B 1M x 1 Bit Static Random Access Memory
MCM6229B 256K x 4 Bit Static Random Access Memory

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM6226BB/D 128K x 8 Bit Static Random Access Memory The MCM6226BB is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. Static design eliminates the need for external clocks or timing strobes while CMOS circuitry reduces power consumption and provides for greater reliability. The MCM6226BB is equipped with both chip enable (E1 and E2) and output enable (G) pins, allowing for greater system flexibility and eliminating bus contention problems. The MCM6226BB is available in 300 mil and 400 mil, 32 lead surface–mount SOJ packages.