Datasheet4U Logo Datasheet4U.com

MCM69P536C - 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle.

chip deselect does not occur when ADSP is

Key Features

  • r Dissipation (See Note 2) Temperature Under Bias Storage Temperature Symbol VDD Vin, Vout Iout PD Tbias Tstg Value.
  • 0.5 to + 4.6.
  • 0.5 to 6.0 ± 20 1.6.
  • 10 to 85.
  • 55 to 125 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to h.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MCM69F737 128K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM NXP
MCM6064 8K x 8-Bit CMOS SRAM Motorola Semiconductor
MCM60L64 8K x 8-Bit CMOS SRAM Motorola Semiconductor
MCM6229A 256K x 4-Bit Static RAM Motorola Semiconductor
MCM6306D 32K x 8-Bit 3.3V Fast Static RAM Motorola Semiconductor

Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MCM69P618C 64K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM69P735 128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM69P736 128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM69P737 128K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM69P817 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69P536C/D 32K x 36 Bit Pipelined BurstRAM Synchronous Fast Static RAM The MCM69P536C is a 1M–bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors. It is organized as 32K words of 36 bits each. This device integrates input registers, an output register, a 2–bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). BiCMOS circuitry reduces the overall power consumption of the integrated functions for greater reliability.