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MCM69P817 - 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM

General Description

Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address.

Used to initiate a READ, WRITE, or chip deselect.

Key Features

  • 6 VSS.
  • 0.5 to VDD VSS.
  • 0.5 to VDD + 0.5 VSS.
  • 0.5 to VDDQ + 0.5 ± 20 1.6.
  • 10 to 85.
  • 55 to 125 Unit V V V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advis.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69P817/D Product Preview MCM69P817 256K x 18 Bit Pipelined BurstRAM™ Synchronous Fast Static RAM The MCM69P817 is a 4M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the PowerPC™ and other high performance microprocessors. It is organized as 256K words of 18 bits each. This device integrates input registers, an output register, a 2–bit address counter, and a high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K).