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MPC2105B - 512KB and 1MB BurstRAM

Download the MPC2105B datasheet PDF. This datasheet also covers the MPC2105A variant, as both devices belong to the same 512kb and 1mb burstram family and are provided as variant models within a single manufacturer datasheet.

General Description

Pin Locations 66, 67, 68, 69, 71, 72, 73, 74, 76, 77, 78, 80, 81, 82, 83, 155, 156, 157, 158, 160, 161, 162, 163, 165, 166, 167, 169, 170, 171 62 151 64, 65 149 172 59, 60 30, 56, 115, 144, 146 153, 154 98, 104, 110, 118, 126, 132, 138, 148 4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26

Key Features

  • ead Cycle, Continue Burst Write Cycle, Suspend Burst Read Cycle, Suspend Burst NOTES: 1. X means Don’t Care. 2. All inputs except CG must meet set.
  • up and hold times for the low.
  • to.
  • high transition of clock (CLK0.
  • CLK4). 3. Wait states are inserted by suspending burst.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (MPC2105A_Motorola.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Motorola Semiconductor (now NXP Semiconductors)

Part Number Description
MPC2105 512KB and 1MB BurstRAM
MPC2105A 512KB and 1MB BurstRAM
MPC2105C 512KB and 1MB BurstRAM
MPC2105P 512KB and 1MB BurstRAM
MPC2104 512KB and 1MB BurstRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2105A/D 512KB and 1MB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2105A/B and the MPC2106A/B are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. The MPC2105A/B and MPC2106A/B utilize synchronous BurstRAMs. The modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM format. The MPC2105A/B uses four of the 3 V 64K x 18; the MPC2106A/B uses eight of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used.