MPC2105P Datasheet | Motorola Semiconductor

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MPC2104P/D Product Preview 256KB/512KB BurstRAM™ Secondary Cache Modules for PowerPC™ PReP/CHRP Platforms The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC mon Hardware Reference Platform (CHRP) specifications. The MPC2104P and MPC2105P utilize synchronous BurstRAMs. The MPC2104P module is configured as 32K x 64 bits and uses two of the 3.3 V 32K x 32 data RAMs. The MPC2105P is configured as 64K x 64 bits and uses two of the 3.3 V 64K x 32 data RAMs. Both...