Description
Differential reference clock frequency input Reference clock input PLL feedback clock input Bank A outputs Bank B outputs Bank C outputs Differential feedback output Reference clock input select Selection of bank A output frequency Selection of bank B output frequency Selection of bank C output freq
Features
- Multiplication of input frequency by 2, 3, 4 and 6.
- Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable.
- Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz.
- Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz.
- LVCMOS outputs.
- Outputs disable to high impedance (except QFB).
- LVCMOS or LVPECL reference clock options.
MPC9600 Datasheet
