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MTB4N80E - TMOS POWER FET

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  • ance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain an.

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Datasheet Details

Part number MTB4N80E
Manufacturer Motorola
File Size 195.75 KB
Description TMOS POWER FET
Datasheet download datasheet MTB4N80E Datasheet
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MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTB4N80E/D ™ Data Sheet TMOS E-FET.™ High Energy Power FET D2PAK for Surface Mount Designer's MTB4N80E Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate The D2PAK package has the capability of housing a larger die than any existing surface mount package which allows it to be used in applications that require the use of surface mount components with higher power and lower RDS(on) capabilities. This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes.
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