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MTV16N50E - TMOS POWER FET 16 AMPERES 500 VOLTS

Key Features

  • obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses. VDS = 0 V VGS = 0 V TJ = 25°C 10000 VGS = 0 V TJ = 25°C Ciss Coss 100 C.

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www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTV16N50E/D Advance Information TMOS E-FET .™ Power Field Effect Transistor D 3 PAK for Surface Mount N–Channel Enhancement–Mode Silicon Gate This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage–blocking capability without degrading performance over time. In addition, this advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diode with a fast recovery time.