Motorola SN74LS175
QUAD D FLIP-FLOP
| Part No. | SN74LS175 |
|---|---|
| Datasheet | SN74LS175 Download |
| Manufacturer |  Motorola |
| Description | QUAD D FLIP-FLOP |
| Buy | Stock & Price |
QUAD D FLIP-FLOP The LSTTL / MSI SN54 / 74LS175 is a high speed Quad D Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when LOW. The LS175 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families.
● Edge-Triggered D-Type Inputs
● Buffered-Positive Edge-Triggered Clock
● Clock to Output Delays of 30 ns
● Asynchronous Common Reset
● True and Complement Output
● Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q3 Q3 D3 D2 Q2 Q2 CP 16 15 14 13 12 11 10 9 1 2 3 4 56 78 MR Q0 Q0 D0 D1 Q1 Q1 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual I
● Edge-Triggered D-Type Inputs
● Buffered-Positive Edge-Triggered Clock
● Clock to Output Delays of 30 ns
● Asynchronous Common Reset
● True and Complement Output
● Input Clamp Diodes Limit High Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q3 Q3 D3 D2 Q2 Q2 CP 16 15 14 13 12 11 10 9 1 2 3 4 56 78 MR Q0 Q0 D0 D1 Q1 Q1 GND NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual I
