DESCRIPTION
The LS175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOW to HIGH Clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The LS175 is useful for general logic applications where a common Master Reset and Clock are acceptable. TRUTH TABLE Inputs (t = n, MR = H) Outputs (t = n+1) Note 1 D Q Q L L H H H L Note 1: t = n + 1 indicates conditions after next clock. DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Parameter Input HIGH Voltage Min Typ Max Unit Test Conditions 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage −0.65 −1.5 V V...
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