CS5821 Overview
Description
CS5821 receives three LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output.
Key Features
- Three 7-bit serial data LVDS channels and one clock LVDS channel
- Compatible with ANSI TIA/EIA-644 LVDS standard
- Wide serial clocking speed ranges from 31MHz to 68MHz
- Support open-safe LVDS design
- Fully integrated on-chip PLL and digital phase alignment provide accurate deserializer operation
- Support power-down mode
- 5V/3.3V tolerant data input
- Single 3.3V supply operation
- CMOS low power consumption
- Available in 48-pin TSSOP package
