Myson Technology CS5825
The clock channel is used for frame sync and fed into an internal PLL that generates the 7X serial clock used in the deserializer. The frame sync clock aligned to the output 7-bit data is also output for timing reference.| Part No. | CS5825 |
|---|---|
| Datasheet | CS5825 Download |
| Manufacturer |  Myson Technology |
| Description | 28:4 LVDS Receiver |
| Buy | Stock & Price |
GENERAL DESCRIPTION
CS5825 receives four LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. A digital phase alignment circuit can generate the sampling clock of the deserializer front-end. CS5825 supports open-safe design of LVDS when the input is not connected to LVDS drivers and the receiver outputs are forced low. Putting CS5825 into inhibit mode by a shutdown control (SHTDNN) signal can lower power consumption.FEATURES
CS5825 28:4 LVDS Receiver● Four 7-bit serial data LVDS channels and one clock LVDS channel.
● Compatible with ANSI TIA/EIA-644 LVDS standard.
● Wide serial clocking speed ranges from 31MHz to 68MHz.
● Support open-safe LVDS design.
● Fully integrated on-chip PLL and digital phase alignment provide accurate deserializer operation.
● Support power-down mode.
● 5V/3.3V tolerant data input.
● Single 3.3V supply operation.
● CMOS low power consumption.
● Functional compatible with DS90CF384 and SN75LVDS86.
