MC-458CA727 Datasheet | NEC

Description The MC-458CA727EFA and MC-458CA727PFA are 8,388,608 words by 72 bits synchronous dynamic RAM module on which 5 pieces of 128M SDRAM : µPD45128163 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction. Features - 8,388,608 words by 72 bits organization (ECC Type) - Clock frequency and access time from CLK Part number /CAS latency Clock frequency (MAX.) MC-458CA727EFA-A75 CL = 3 CL = 2 MC-458CA727PFA-A75 CL = 3 CL = 2 133 MHz 100 MHz 133 MHz 100 MHz Access time from CLK (MAX.) 5.4 ns 6.0 ns 5.4 ns 6.0 ns 5 5 5 - Pulsed interface - Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge - Possible to assert random column address in every cycle - Quad internal banks controlled by BA0 and BA1 (Bank Select) - Programmable burst-length (1, 2, 4, 8 and full page) - Programmable wrap sequence (sequential / interleave) 5 - Programmable /CAS latency (2, 3) - Automatic precharge and controlled precharge - CBR (Auto) refresh and self refresh - All DQs have 10 Ω ± 10 % of series resistor - Single 3.3 V ± 0.3 V power supply - LVTTL patible - 4,096 refresh cycles /64 ms - Burst termination by Burst Stop mand and Precharge mand - 168-pin dual in-line memory module (Pin pitch = 1.27 mm) - Unbuffered type - Serial PD The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M14278EJ3V0DS00 (3rd edition) Date Published January 2000 NS CP(K) Printed in Japan The mark - shows major revised points. © Ordering Information Part number Clock frequency (MAX.) MC-458CA727EFA-A75 133 MHz 168-pin Dual...