NEC UPD16602
This pin reads the start pulse at the rising of CLK and starts sampling of analog display signals in 12 channels simultaneously. The active edges of CLK are all rising edges.| Part No. | UPD16602 |
|---|---|
| Datasheet | UPD16602 Download |
| Manufacturer |  NEC |
| Description | 312-OUTPUT TFT-LCD FULL COLOR DRIVER |
| Buy | Stock & Price |
FEATURES
● 4 × 3 (RGB)-channel analog input allows display signal input wiring to be reduced.● High dynamic range (10.0 VP-PMIN. VDD2 = 11.0 V)
● High accuracy sample & hold circuits (output deviation; ±20 mVMAX., ±5.0 mVTYP.)
● High-speed sampling frequency (for both analog and digital; fmax. = 20 MHzMIN.)
● Low power control (reduction of output buffer bias current) function on chip (operating power consumption; 82 mWTYP., VDD2 = 12.5 V)
● Bi-directional data store function on chip
● Corresponding to high-density mounting (slim TCP) ORDERING INFORMATION Part Number µPD16602N- × × × TCP Package Document No. S10671EJ1V0DS00 (1st edition) Date Published August 1998 N CP(K) Printed in Japan © 1998 1. BLOCK DIAGRAM R/L CLK SPR S/D 1 2 Bi-directional shift register (26 circuits) DR0 to DR3 DG0 to DG3 DB0 to DB3 1 2 1 2 Level shifter (26 circuits) 4 4 4 PL/NL HS BIAS1 BIAS2 Sample & hold + output buffer circuit S1 SAMPLE & HOLD + OUTPUT BUFFER CIRCUIT 1 µPD16602 SPL 26 VDD1 VSS1 VDD2(D) 26...
