UPD16602 Description
Pin Symbol S1 to S312 CLK DR0 to DR3 DG0 to DG3 DB0 to DB3 R/L SPR SPL Note PL/NL S/D Note HS LPC BIAS1 BIAS2 VDD1 VDD2(D) VDD2(A) V VSS1 VSS2(D) VSS2(A) VSS2(C) TEST Pin Name Driver outputs Clock input Analog display signal inputs Description Output pins for.
UPD16602 Key Features
- 4 × 3 (RGB)-channel analog input allows display signal input wiring to be reduced
- High dynamic range (10.0 VP-PMIN. VDD2 = 11.0 V)
- High accuracy sample & hold circuits (output deviation; ±20 mVMAX., ±5.0 mVTYP.)
- High-speed sampling frequency (for both analog and digital; fmax. = 20 MHzMIN.)
- Low power control (reduction of output buffer bias current) function on chip
- Bi-directional data store function on chip
- Corresponding to high-density mounting (slim TCP)