UPD30500A Overview
The µPD30500 (VR5000), µPD30500A (VR5000A), and µPD30500BNote (VR5000B) are a high-performance, 64bit RISC (Reduced Instruction Set puter) type microprocessors employing the RISC architecture developed by MIPSTM Technologies Inc. The instructions of the VR5000, VR5000A, and VR5000B are patible with those of the VR3000TM Series and VR4000TM Series and higher, and pletely patible with those of the VR10000TM....
UPD30500A Key Features
- Employs 64-bit MIPS-based RISC architecture
- High-speed processing
- 2-way super scalar 5-stage pipeline
- High-speed translation buffer mechanism (TLB) (48 entries)
- Address space Physical: 36 bits, Virtual: 40 bits
- Floating-point unit (FPU)
- Sum-of-products operation instruction supported
- Primary cache memory (instruction/data: 32 Kbytes each)
- Secondary cache controller
- Maximum operating frequency Internal: 200 MHz (µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B) External: 100 MHz