UPD4104 Description
Organized as 4096 x 1, it uses a bination of static storage cells with dynamic input/output circuitry to achieve high speed and low power in the same device. Utilizing NMOS technology, the J.LPD4104 is fully TTL patible and operates with a single +5V ± 10% supply.
UPD4104 Key Features
- Very Low Stand-By Power
- 28 mW Max
- Low VCC Data Retention Mode to +3 Volts
- Single +5V ±10% Supply
- Fully TTL patible
- Available in 18 Pin Plastic and Ceramic Dual-in-Line Packages
- '3 Performance Ranges