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UPD44164364 - (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION

This page provides the datasheet information for the UPD44164364, a member of the UPD44164084 (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION family.

Datasheet Summary

Description

technology using full CMOS six-transistor memory cell.

Features

  • 1.8 ± 0.1 V power supply and HSTL I/O.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Pipelined double data rate operation.
  • Common data input/output bus.
  • Four-tick burst for reduced address frequency.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving d.

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Datasheet preview – UPD44164364

Datasheet Details

Part number UPD44164364
Manufacturer NEC
File Size 394.10 KB
Description (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION
Datasheet download datasheet UPD44164364 Datasheet
Additional preview pages of the UPD44164364 datasheet.

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Other Datasheets by NEC
  • UPD44164362 - (UPD44164082/182/362) 18M-BIT DDRII SRAM 2-WORD BURST OPERATION
  • UPD44164365 - (UPD44164085/185/365) 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
  • UPD44164082 - (UPD44164082/182/362) 18M-BIT DDRII SRAM 2-WORD BURST OPERATION
  • UPD44164084 - (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION
  • UPD44164085 - (UPD44164085/185/365) 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
  • UPD44164182 - (UPD44164082/182/362) 18M-BIT DDRII SRAM 2-WORD BURST OPERATION
  • UPD44164184 - (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION
  • UPD44164185 - (UPD44164085/185/365) 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION

Full PDF Text Transcription

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DATA SHEET MOS INTEGRATED CIRCUIT µPD44164084, 44164184, 44164364 18M-BIT DDRII SRAM 4-WORD BURST OPERATION Description The µPD44164084 is a 2,097,152-word by 8-bit, the µPD44164184 is a 1,048,576-word by 18-bit and the µPD44164364 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44164084, µPD44164184 and µPD44164364 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.
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