UPD4481361 Description
The µPD4481161, µPD4481181, µPD4481321 and µPD4481361 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
UPD4481361 Key Features
- Synchronous operation
- 100 percent bus utilization
- Internally self-timed write control
- Burst read / write : Interleaved burst and linear burst sequence
- Fully registered inputs and outputs for flow through operation
- All registers triggered off positive clock edge
- 3.3V or 2.5V LVTTL patible : All inputs and outputs
- Fast clock access time : 6.5 ns (133 MHz), 7.5 ns (117 MHz), 8.5 ns (100 MHz)
- Asynchronous output enable : /G
- Burst sequence selectable : MODE