Datasheet4U Logo Datasheet4U.com

UPD4482182 - (UPD4482162/2182/2322/2362) 8M-BIT CMOS SYNCHRONOUS FAST SRAM

This page provides the datasheet information for the UPD4482182, a member of the UPD4482162 (UPD4482162/2182/2322/2362) 8M-BIT CMOS SYNCHRONOUS FAST SRAM family.

Datasheet Summary

Description

The µPD4482162 is a 524,288-word by 16-bit, the µPD4482182 is a 524,288-word by 18-bit, µPD4482322 is a 262,144word by 32-bit and the µPD4482362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell.

Features

  • 3.3 V or 2.5 V core supply.
  • Synchronous operation.
  • Operating temperature : TA = 0 to 70 °C (-A44, -A50, -A60, -C60) TA =.
  • 40 to +85 °C (-A44Y, -A50Y, -A60Y, -C60Y).
  • Internally self-timed write control.
  • Burst read / write : Interleaved burst and linear burst sequence.
  • Fully registered inputs and outputs for pipelined operation.
  • Single-Cycle deselect timing.
  • All registers triggered off positive clock edge.
  • 3.

📥 Download Datasheet

Datasheet preview – UPD4482182

Datasheet Details

Part number UPD4482182
Manufacturer NEC
File Size 445.13 KB
Description (UPD4482162/2182/2322/2362) 8M-BIT CMOS SYNCHRONOUS FAST SRAM
Datasheet download datasheet UPD4482182 Datasheet
Additional preview pages of the UPD4482182 datasheet.
Other Datasheets by NEC

Full PDF Text Transcription

Click to expand full text
DATA SHEET MOS INTEGRATED CIRCUIT µPD4482162, 4482182, 4482322, 4482362 8M-BIT CMOS SYNCHRONOUS FAST SRAM PIPELINED OPERATION SINGLE CYCLE DESELECT Description The µPD4482162 is a 524,288-word by 16-bit, the µPD4482182 is a 524,288-word by 18-bit, µPD4482322 is a 262,144word by 32-bit and the µPD4482362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology using Full-CMOS six-transistor memory cell. The µPD4482162, µPD4482182, µPD4482322 and µPD4482362 integrates unique synchronous peripheral circuitry, 2bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single clock input (CLK).
Published: |