UPD720100A Description
DATA SHEET MOS INTEGRATED CIRCUIT µPD720100A USB2.0 HOST CONTROLLER The µPD720100A plies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720100A is integrated three host controller cores with PCI interface and...
UPD720100A Key Features
- pliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
- pliant with Open Host Controller Interface Specification for USB Rev 1.0a
- pliant with Enhanced Host Controller Interface Specification for USB Rev 0.95
- PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI host con
- Root hub with five (max.) downstream facing ports which are shared by OHCI and EHCI host controller core
- All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction
- Configurable number of downstream facing ports (2 to 5)
- 32-bit 33 MHz host interface pliant to PCI Specification release 2.2
- Supports PCI Mobile Design Guide Revision 1.1
- Supports PCI-Bus Power Management Interface Specification release 1.1