UPD72850A
Key Features
- The Three-port Physical Layer LSI complies to IEEE P1394a draft 2.0
- Connection debounce
- Arbitration enhancements
- Arbitrated short bus reset
- Ack-accelerated arbitration
- Fly-by concatenation
- Multiple-speed packet concatenation
- Arbitration enhancements and cycle start (controlled by the Link layer)
- Performance optimization via PHY pinging
- Priority arbitration (controlled by the Link layer)
