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PA102FDG - P-Channel Logic Level Enhancement

Download the PA102FDG datasheet PDF. This datasheet also covers the PA102FDG-NIKO variant, as both devices belong to the same p-channel logic level enhancement family and are provided as variant models within a single manufacturer datasheet.

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Note: The manufacturer provides a single datasheet file (PA102FDG-NIKO-SEM.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PA102FDG
Manufacturer NIKO-SEM
File Size 261.06 KB
Description P-Channel Logic Level Enhancement
Datasheet download datasheet PA102FDG Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor PA102FDG TO-252 Lead-Free PRODUCT SUMMARY V(BR)DSS RDS(ON) -20 115m ID -10A D G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current1 TC = 25 °C TC = 70 °C Power Dissipation TC = 25 °C TC = 70 °C Operating Junction & Storage Temperature Range VDS VGS ID IDM PD Tj, Tstg THERMAL RESISTANCE RATINGS THERMAL RESISTANCE SYMBOL TYPICAL Junction-to-Case RθJC Junction-to-Ambient RθJA 1Pulse width limited by maximum junction temperature. 2Duty cycle ≤ 1% 1 :GATE 2 :DRAIN 3 :SOURCE LIMITS -20 ±12 -10 -6.2 -24 25 9.