74AUP1G07 Datasheet Low-power Buffer

Manufacturer: NXP Semiconductors

Overview: www.DataSheet4U.com 74AUP1G07 Low-power buffer with open-drain output Rev. 02 — 14 June 2007 Product data sheet 1.

Datasheet Details

The 74AUP1G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept.

Part Number	Description	Manufacturer
74AUP1G07	SINGLE BUFFER/DRIVER	Diodes
74AUP1G07	Low-power buffer	nexperia
74AUP1G07-Q100	Low-power buffer	nexperia

Part Number	Description
74AUP1G00	Low-power 2-input NAND gate
74AUP1G04	Low-power inverter
74AUP1G06	Low-power inverter
74AUP1G08	Low-power 2-input AND gate
74AUP1G125	Low-power buffer/line driver
74AUP1G373	Low-power D-type transparent latch
74AUP1G386	Low-power 3-input EXCLUSIVE-OR gate
74AUP1GU04	Low-power unbuffered inverter
74AUP2G07	Low-power dual buffer
74AUP2G125	Low-power dual buffer/line driver