74AUP1G125 - Low-power buffer/line driver

Product Overview

NXP Semiconductors

Part number	74AUP1G125
Manufacturer	NXP Semiconductors
File Size	141.24 KB
Description	Low-power buffer/line driver
Datasheet	74AUP1G125 Datasheet
Additional preview pages of the 74AUP1G125 datasheet.

The 74AUP1G125 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8-12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V to 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2.7 V to 3.6 V) I ESD protection: N HBM JESD22-A114-C Class 3A. Exceeds 5000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101-C exceeds 1000 V I Low static power consumption; ICC = 0.9 µA (maximum) I Latch-up performance exceeds 100 mA per JESD 78 Class II I Inputs acce.

📁 Similar Datasheet

Other Datasheets by NXP Semiconductors

Published: Apr 28, 2010 |