74LVC1G74 Datasheet | NXP Semiconductors

description The 74LVC1G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and plementary Q and Q outputs. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity plies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 m A output drive (VCC = 3.0 V) ESD protection: x HBM EIA/JESD22-A114E exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 m A Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from - 40 °C to +85 °C and - 40 °C to +125 °C s s s s s s s s NXP Semiconductors .. Single D-type flip-flop with set and reset; positive edge trigger 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC1G74DP 74LVC1G74DC 74LVC1G74GT 74LVC1G74GM - 40 °C to +125 °C - 40 °C to +125 °C - 40 °C to +125 °C - 40 °C to +125 °C TSSOP8 VSSOP8 XSON8 XQFN8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; body width 2.3 mm plastic extremely thin small outline package; no leads; 8 terminals;...